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IS31FL3728 integrated silicon solution, inc. ? www.issi.com 1 rev.a, 12/19/2011 audio modulated matrix led driver december 2011 general description IS31FL3728 is a general purpose 88 led matrix driver which features an audio frequency equalizer (eq) mode or a general led dot matrix display mode. the general led matrix display defaults to an 88 configuration, however, it can be configured for a 511, 610, 79 dot matrix display. the matrix picture brightness can be modulated by audio. in either the audio eq mode or matrix display mode, the array is internally scanned, and requires only one-time programming, thus eliminating the need for real time system resource utilization. it programs the led array through i2c interface. in the general purpose display mode, each dot of the led array is independently programmed on or off over time. in the audio eq mode, the x axis (column) represents the frequency bands while the y axis (row) represents the strength of the input audio signal in each band. the number of leds lit in a column is proportional to the strength of the audio signal in the corresponding band in a thermometer-coded manner. IS31FL3728 is available in 24-pin qfn (4mm 4mm). it operates from 2.7v to 5.5v over the temperature range of -40c to +85c. features ? 5~8 current source outputs for row control ? 8~11 outputs for column scan control ? programmable 88, 79, 610, 511 matrix ? one-time programming, internal scan ? full scale led current controlled by internal register setting or audio signal ? audio frequency eq display with programmable input gain ? led matrix brightness can be modulated with audio signal ? one address pin with 4 logic levels to allow four i2c slave addresses ? i2c interface ? 2.7v to 5.5v supply ? over-temperature protection ? qfn-24 (4mm 4mm) package applications ? mobile phones and other hand-held devices for led displays. ? audio frequency equalizer display typical application circuit figure 1 typical application circuit
IS31FL3728 integrated silicon solution, inc. ? www.issi.com 2 rev.a, 12/19/2011 pin configuration package pin configuration (top view) qfn-24 pin description no. pin description 1 sda serial data. 2 scl serial clock. 3 sdb shutdown the chip when pull to low. 4 in audio input. 5 c_filt low pass filter cap for audio control. 6 ad i2c address setting. 7~10, 12 r1~r5 current source outputs. 11 vcc power supply. 13~15 r6/c11, r7/c10, r8/c9 cmos outputs. 16~19,21~24 c8~c1 current sink outputs. 20 gnd ground. thermal pad connect to gnd. copyright ? ? ? 2011 ? integrated ? silicon ? solution, ? inc. ? all ? rights ? reserved. ? issi ? reserves ? the ? right ? to ? make ? changes ? to ? this ? specification ? and ? its ? products ? at ? any time ? without ? notice. ? issi ? assumes ? no ? liability ? arising ? out ? of ? the ? application ? or ? use ? of ? any ? information, ? products ? or ? services ? described ? herein. ? customers ? are ? advised ? to ? obtain ? the ? latest ? version ? of ? this ? device ? specification ? before ? relying ? on ? any ? published ? information ? and ? before ? placing ? orders ? for ? products. ? integrated ? silicon ? solution, ? inc. ? does ? not ? recommend ? the ? use ? of ? any ? of ? its ? products ? in ? life ? support ? applications ? where ? the ? failure ? or ? malfunction ? of ? the ? product ? can ? reasonably ? be ? expected ? to ? cause ? failure ? of ? the ? life ? support ? system ? or ? to ? significantly ? affect ? its ? safety ? or ? effectiveness. ? products ? are ? not ? authorized ? for ? use ? in ? such ? applications ? unless ? integrated ? silicon ? solution, ? inc. ? receives ? written ? assurance ? to ? its ? satisfaction, ? that: ? a.) ? the ? risk ? of ? injury ? or ? damage ? has ? been ? minimized; ? b.) ? the ? user ? assume ? all ? such ? risks; ? and ? c.) ? potential ? liability ? of ? integrated ? silicon ? solution, ? inc ? is ? adequately ? protected ? under ? the ? circumstances
IS31FL3728 integrated silicon solution, inc. ? www.issi.com 3 rev.a, 12/19/2011 ordering information industrial range: -40c to +85c order part no. package qty/reel IS31FL3728-qfls2-tr qfn-24, lead-free 2500
IS31FL3728 integrated silicon solution, inc. ? www.issi.com 4 rev.a, 12/19/2011 absolute maximum ratings supply voltage, v cc - 0.3v ~ +6.0v voltage at any input pin - 0.3v ~ v cc +0.3v maximum junction temperature, t jmax 150c storage temperature range, t stg - 65c ~ +150c operating temperature range, t a ? 40c ~ +85c note: stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress rating s only and functional operation of the device at these or any other condition beyond those indicated in the operational sections of th e specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. electrical characteristics t a = -40c ~ +85c, unless otherwise noted. typical value are t a = +25c. symbol parameter condition min. typ. max. unit v cc supply voltage 2.7 5.5 v i cc quiescent power supply current v in = 0v, register cd1:cd11 = 0 dot matrix display mode without audio modulation 4.1 5.0 ma i sd shutdown current v sdb = 0v 0.2 1.0 a v sdb = 5v software shutdown 1.7 3.0 a i out output current of r1~r8 dot matrix display mode without audio modulation 42.8 (note 1) ma dot matrix display mode with audio modulation v in = 1.8vp-p, 1khz square wave, audio gain = 0db 42.3 (note 1) ma v hr current sink (i sink , c1:c8) headroom voltage and current source (i out , r1:r8) headroom voltage i sink = 320ma (note 2) 300 mv i out = 40ma 200 logic electrical characteristics v in(0) logic ?0? input voltage v cc = 2.7v 0.4 v v in(1) logic ?1? input voltage v cc = 5.5v 1.4 v i in(0) logic ?0? input current v in = 0v 5 (note 3) na i in(1) logic ?1? input current v in = v cc 5 (note 3) na
IS31FL3728 integrated silicon solution, inc. ? www.issi.com 5 rev.a, 12/19/2011 digital input switching characteristics (note 3) symbol parameter condition min. typ. max. unit f scl serial-clock frequency 400 khz t buf bus free time between a stop and a start condition 1.3 s t hd, sta hold time (repeated) start condition 0.6 s t su, sta repeated start condition setup time 0.6 s t su, sto stop condition setup time 0.6 s t hd, dat data hold time 0.9 s t su, dat data setup time 100 ns t low scl clock low period 1.3 s t high scl clock high period 0.7 s t r rise time of both sda and scl signals, receiving (note 4) 20 + 0.1cb 300 ns t f fall time of both sda and scl signals, receiving (note 4) 20 + 0.1cb 300 ns note 1: current of single led in rx(x=1~8) is i out /8. note 2: all row drivers are on. note 3: guaranteed by design. note 4: cb = total capacitance of one bus line in pf. i sink 6ma. t r and t f measured between 0.3 v cc and 0.7 v cc .
IS31FL3728 integrated silicon solution, inc. ? www.issi.com 6 rev.a, 12/19/2011 detailed description i2c interface the IS31FL3728 uses a serial bus, which conforms to the i2c protocol, to control the chip?s functions with two wires: scl and sda. the IS31FL3728 has a 7-bit slave address (a6:a0). the bit a1 and bit a0 are decided by the connection of ad pin. the complete slave address is: table 1 slave address (write only) ad connects to a6:a2 a1 a0 r/ w ____ gnd 11000 0 0 0 (write only) vcc 1 1 scl 0 1 sda 1 0 the scl line is uni-directional. the sda line is bi-directional (open-collector) with a pull-up resistor (typically 4.7k ? ). the maximum clock frequency specified by the i2c standard is 400 khz. in this discussion, the master is the microcontroller and the slave is the IS31FL3728. the timing diagram for the i2c is shown in figure 3. the sda is latched in on the stable high level of the scl and the sda line should be held high when not in use. the ?start? signal is generated by lowering the sda signal while the scl signal is high. the start signal will alert all devices attached to the i2c bus to check the incoming address against their own chip address. the 8-bit chip address is sent next, most significant bit first. each address bit must be stable while the scl level is high. after the last bit of the chip address is sent, the master checks for the IS31FL3728?s acknowledge. the master releases the sda line high (through a pull-up resistor). then the master sends an scl pulse. if the IS31FL3728 has received the address correctly, then it holds the sda line low during the scl pulse. if the sda line is not low, then the master should send a ?stop? signal (discussed later) and abort the transfer. following acknowledge of IS31FL3728, the register address byte is sent, most significant bit first. IS31FL3728 must generate another acknowledge indicating that the register address has been received. then 8 bits of data byte is sent, most significant bit first. each data bit should be valid while the scl level is stable high. after the data byte is sent, the IS31FL3728 must generate another acknowledge indicating that the data has been received. if the master has more data bytes to send to the IS31FL3728, then the master can repeat the previous two steps until all data bytes have been sent. the ?stop? signal ends the transfer. to signal ?stop?, the sda signal goes high while the scl signal is high. figure 2 writing to IS31FL3728 figure 3 interface timing figure 4 bit transfer
IS31FL3728 integrated silicon solution, inc. ? www.issi.com 7 rev.a, 12/19/2011 registers definition 00h configuration register bit d7 d6:d3 d2 d1 d0 name ssd - audio_en adm default 0 0000 0 0 0 the configuration register sets operation mode of IS31FL3728. ssd software shutdown enable 0 normal operation 1 software shutdown mode audio_en audio input enable 0 matrix intensity is controlled by the current setting in the lighting effect register (0dh) 1 enable audio signal to modulate the intensity of the matrix in dot matrix display mode adm array mode selection 00 88 dot matrix display mode 01 79 dot matrix display mode 10 610 dot matrix display mode 11 511 dot matrix display mode 01h~0bh column data register (cd1~cd11) bit d7:d0 name r8:r1 default 00000000 the column data registers store the on or off state of each led in the array. rx led state 0 led off 1 led on the data in the column data registers is valid only when the chip is configured in general purpose dot matrix display mode. 11 registers are assigned to cd1~cd11 columns respectively; the led at a particular (row, column) location will be turned on when the respective data is set to 1. when configured to other than 88 dot matrix display mode operation, only the required number of lsbs is used in each column register. for example, in 511 dot matrix display mode, only bits r5 through r1 are used, and bits r8 through r6 are ignored. 0ch update column register the data sent to the column data registers will be stored in temporary registers. a write operation of any 8-bit value to the update column register is required to update the column data registers (01h: 0bh). 0dh lighting effect register bit d7 d6:d4 d3:d0 name - ags cs default 0 000 0000 the lighting effect register stores the intensity control settings for all of the leds in the array ags audio input gain selection 000 0db 001 +3db 010 +6db 011 +9db 100 +12db 101 +15db 110 +18db 111 -6db cs full current setting for each row output 0000 40ma 0001 45ma ... ... 0111 75ma 1000 5ma 1001 10ma ... ... 1110 35ma 0fh audio_eq register bit d7 d6 d5:d0 name - ae_en - default 0 0 000000 the audio_eq register enables the audio frequency equalizer (audio eq) mode ae_en audio eq mode 0 disable 1 enable
IS31FL3728 integrated silicon solution, inc. ? www.issi.com 8 rev.a, 12/19/2011 application information audio frequency equalizer (audio eq) mode the IS31FL3728 features audio frequency equalizer mode, or audio eq mode. the current of the matrix is adjusted by lighting effect register as dot matrix display mode. in the audio eq mode, only 8 columns are valid and display the three bands of the audio signal. when the IS31FL3728 is configured as 79, 610 or 511, only columns c1 thru c8 will be used, and the remaining columns will always be off. signal strength figure 5 audio eq mode general purpose dot matrix display mode the general purpose dot matrix display timing diagram is shown in figure 6. the IS31FL3728 is configured as general purpose 88 dot matrix display mode at initial power up. column controls c[8:1] scans the eight columns at a rate of 3.79khz, or 264us per frame. each column is effective for 32us. the non-overlap interval between adjacent columns is 1us. the IS31FL3728 also can be configured as 79, 610 or 511 dot matrix display mode. the frame period is changed slightly depending on the number of columns required to scan by an additional time of 33us per column. for example, when in 79 dot matrix display mode, the column data registers? msb will be invalid and column controls c[9:1] scans the nine columns 297us per frame. c1 c2 c3 cn n=8~11 32us 1us load column data at each rising edge column data 1 column data 2 column data 3 column data n row output column data 1 figure 6 dot matrix display timing diagram 8 8 dot matrix display mode the application example in figure 1 shows the IS31FL3728 in the 88 led dot matrix display mode. the led columns have common cathodes and are connected to the c1:c8 outputs. the rows are connected to the row drivers. each of the 64 leds can be addressed separately. the columns are selected via the registers 01h~08h as described in the registers definition section. 511 dot matrix display mode by setting d1&d0 of the configuration register to 11, the IS31FL3728 will operate in the 511 led dot matrix display mode. the led columns have common cathodes and are connected to the c1:c11 outputs. the rows are connected to the row drivers. each of the 55 leds can be addressed separately. the three msbs of each register, r8~r6, are ignored. the columns are selected via the registers as described in the registers definition section. dot matrix display mode with audio modulation when the IS31FL3728 operates in any of the dot matrix modes, if the bit audio_en in configuration register is set to 1, the panel will get the effect of audio modulation initial power-up on initial power-up, the IS31FL3728 registers are reset to their default values for a blank display. at this time, all registers should be programmed for the desired operation.
IS31FL3728 integrated silicon solution, inc. ? www.issi.com 9 rev.a, 12/19/2011 software shutdown mode the IS31FL3728 devices feature a software shutdown mode, wherein they consume only 1.7 a (typ.) current. shutdown mode is entered via a write to the configuration register. when the IS31FL3728 is in shutdown mode, all current sources and digital drivers are switched off, so that the array is blanked. shutdown mode can either be used as a means of reducing power consumption or generating a flashing display (repeatedly entering and leaving shutdown mode). note: during shutdown mode all registers retain their data.
IS31FL3728 integrated silicon solution, inc. ? www.issi.com 10 rev.a, 12/19/2011 classification reflow profiles profile feature pb-free assembly preheat & soak temperature min (tsmin) temperature max (tsmax) time (tsmin to tsmax) (ts) 150c 200c 60-120 seconds average ramp-up rate (tsmax to tp) 3c/second max. liquidous temperature (tl) time at liquidous (tl) 217c 60-150 seconds peak package body temperature (tp)* max 260c time (tp)** within 5c of the specified classification temperature (tc) max 30 seconds average ramp-down rate (tp to tsmax) 6c/second max. time 25c to peak temperature 8 minutes max. figure 7 classification profile
IS31FL3728 integrated silicon solution, inc. ? www.issi.com 11 rev.a, 12/19/2011 tape and reel information
IS31FL3728 integrated silicon solution, inc. ? www.issi.com 12 rev.a, 12/19/2011 package information qfn-24 note: all dimensions in millimeters unless otherwise stated.

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